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M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0088-0122 Rev.1.22 Mar 30, 2007
1.
Overview
The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. In addition, these microcomputers contain a multiplier and DMAC which combined with fast instruction processing capability, make it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/ logic operations.
1.1
Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 1 of 53
M16C/30P Group
1. Overview
1.2
Performance Outline
Table 1.1 lists Performance Outline of M16C/30P Group. Table 1.1 CPU Performance Outline of M16C/30P Group
Item Performance Number of Basic Instructions 91 instructions Minimum Instruction 62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no wait) Execution Time 100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait) Operation Mode Single-chip, memory expansion and microprocessor mode Memory Space 1 Mbyte Memory Capacity See Table 1.2 Product List Peripheral Port Input/Output : 87 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 3 channels, Timer B : 16 bits x 3 channels Serial Interface 1 channels Clock synchronous, UART, I2CBus(1), IEBus(2) 2 channels Clock synchronous, UART, I2CBus(1) A/D Converter 10-bit A/D converter: 1 circuit, 18 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 20 sources, External: 7 sources, Software: 4 sources, Priority level: 7 levels Clock Generating Circuit 2 circuits Main clock generation circuit (*), Subclock generation circuit (*), (*)Equipped with a built-in feedback resistor. Electric Supply Voltage VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz) Characteristics VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait) Power Consumption 10 mA (VCC1=VCC2=5V, f(XIN)=16MHz) 8 mA (VCC1=VCC2=3V, f(XIN)=10MHz) 1.8 A (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7 A(VCC1=VCC2=3V, stop mode) One time flash Program Supply Voltage 3.30.3 V or 5.00.5 V version Flash memory Program/Erase Supply 3.30.3 V or 5.00.5 V version Voltage Program and Erase 100 times (all area) Endurance Operating Ambient Temperature -20 to 85C, -40 to 85C Package 100-pin plastic mold QFP, LQFP
NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. Use the M16C/30P on VCC1 = VCC2.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
1.3
Block Diagram
Figure 1.1 is a M16C/30P Group Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
8
Internal peripheral functions
A/D converter
Timer (16-bit) Output (timer A): 3 Input (timer B): 3
(10 bits X 18 channels)
UART or clock synchronous serial I/O
System clock generation circuit XIN-XOUT XCIN-XCOUT
Port P8
7
(3 channels)
Port P8_5
CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core Watchdog timer
(15 bits)
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
Port P9
ROM (1) RAM (2)
8
DMAC
(2 channels)
Port P10
8
Multiplier
NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type.
Figure 1.1
M16C/30P Group Block Diagram
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
1.4
Product List
Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table 1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of Mask ROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P. Figure 1.4 shows the Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less Version for M16C/30P (Top View). Please specify the marking for M16C30P (MASK ROM version) when placing an order for ROM. Table 1.2 Product List (1)
ROM Capacity 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 96 Kbytes (D) 128 Kbytes (D) 160 Kbytes (D) (D) (D) 192 Kbytes (D) (D) (D) (D) (D) (D) 128 Kbytes (D) 160 Kbytes (D) (D) (D) 192 Kbytes (D) (D) (D) (D) (D) 6 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 256 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 6 Kbytes 12 Kbytes 256 Kbytes 96 Kbytes 12 Kbytes 5 Kbytes 5 Kbytes 6 Kbytes RAM Capacity 5 Kbytes package code PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A
(1)
As of March 2007 Remarks Mask ROM version
Part No. M30302MAP-XXXFP M30302MAP-XXXGP M30302MCP-XXXFP M30302MCP-XXXGP M30302MDP-XXXFP M30302MDP-XXXGP M30302MEP-XXXFP M30302MEP-XXXGP M30302GAPFP M30302GAPGP M30302GCPFP M30302GCPGP M30302GDPFP M30302GDPGP M30304GDPFP M30304GDPGP M30302GEPFP M30302GEPGP M30304GEPFP M30304GEPGP M30302GGPFP M30302GGPGP M30302GAP-XXXFP M30302GAPvGP M30302GCP-XXXFP M30302GCP-XXXGP M30302GDP-XXXFP M30302GDP-XXXGP M30304GDP-XXXFP M30304GDP-XXXGP M30302GEP-XXXFP M30302GEP-XXXGP M30304GEP-XXXFP M30304GEP-XXXGP M30302GGP-XXXFP M30302GGP-XXXGP
One Time Flash version (blank product)
One Time Flash version (factory programmed product)
(D): Under development (P): Under planning NOTES: 1. Previous package codes are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A 2. Block A (4-Kbytes space) is available in flash memory version.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group Table 1.3 Product List (2)
ROM Capacity 96 K + 4 Kbytes 128 K + 4 Kbytes 192 K + 4 Kbytes 6 Kbytes 6 Kbytes RAM Capacity 5 Kbytes package code (1) PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A
1. Overview
As of March 2007 Remarks Flash memory version(2)
Part No. M30302FAPFP M30302FAPGP M30302FCPFP M30302FCPGP M30302FEPFP M30302FEPGP M30302SPFP M30302SPGP
ROM-less version
(D): Under development (P): Under planning NOTES: 1. Previous package codes are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A 2. Block A (4-Kbytes space) is available in flash memory version.
Part No.
M3030 2 M E P- XXX HP
Package type: FP : Package PRQP0100JB-A (100P6S-A) GP : Package PLQP0100KB-A (100P6Q-A) ROM No. M16C/30P Group ROM A C D E G capacity: : 96 Kbytes : 128 Kbytes : 160 Kbytes : 192 Kbytes : 256 Kbytes
Memory type: M : Mask ROM version G : One Time Flash version F : Flash Memory version S : ROM-less version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/30 Series M16C Family
Figure 1.2
Part No., Memory Size, and Package
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
Table 1.4
Product Code U1 U4
Product Code of MASK ROM version for M16C/30P
Package Lead-free Operating Ambient Temperature -20C to 85C -40C to 85C
PRQP0100JB-A (100P6S-A)
1. Standard Renesas Mark
M1 6C M3 0 3 0 2 M D P - X X X F P A U1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version, product code and date code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) XXXXXXX : Seven digits
2. Customer's Parts Number + Renesas catalog name
M3 0 3 0 2 M D P - X X X F P A U1 M1 6 C X X X X X X X
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
PLQP0100KB-A (100P6Q-A)
1. Standard Renesas Mark
M1 6C M 3 0 3 0 2 MD P - X X XGP A U 1 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version, product code and date code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) XXXXXXX : Seven digits
2. Customer's Parts Number + Renesas catalog name
M 3 0 3 0 2 MD P A U1 - X X XGP M1 6 C XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U1 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
NOTES: 1. Refer to the mark specification form for details of the Mask ROM version marking.
Figure 1.3
Marking Diagram of Mask ROM Version for M16C/30P (Top View) Page 6 of 53
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
M16C/30P Group
1. Overview
Table 1.5
Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P
Internal ROM
Product Code One Time Flash version Flash Memory version ROM-less version U3 U5 U3 U5 U3 U5
Package
Program and Erase Endurance 0 100
-
Temperature Range 0C to 60C
Operating Ambient Temperature -40C to 85C -20C to 85C -40C to 85C -20C to 85C -40C to 85C -20C to 85C
Leadfree Leadfree Leadfree
0C to 60C -
NOTES:The one time flash version can be written once only.
PRQP0100JB-A (100P6S-A) M1 M3 03 0 2SP A XXXXX 6 F U X C P 3 X
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U3 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
PLQP0100KB-A (100P6Q-A)
M1 6C M 3 0 3 0 2 S PGP A U3 XXXXXXX
Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version and product code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C. U3 : Shows Product code. (See table 1.3 Product Code) Date code seven digits
The product without marking of chip version of One Time Flash version, Flash Memory version, and the ROMless version corresponds to the chip version "A".
Figure 1.4
Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less Version for M16C/30P (Top View)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
1.5
Pin Configuration
Figures 1.5 to 1.6 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15 P2_0/A0 P2_1/A1 P2_2/A2 P2_3/A3 P2_4/A4 P2_5/A5 P2_6/A6 P2_7/A7 VSS P3_0/A8 VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
M16C/30P Group
P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1
NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2.
Figure 1.5
Pin Configuration (Top View)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
P9_6/ANEX1 P9_5/ANEX0 P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN P7_2/CLK2/TA1OUT P7_1/RXD2/SCL2/TA0IN (1) P7_0/TXD2/SDA2/TA0OUT (1)
Package : PRQP0100JB-A (100P6S-A)
Page 8 of 53
M16C/30P Group
1. Overview
PIN CONFIGURATION (top view)
P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15 P2_0/A0 P2_1/A1 P2_2/A2 P2_3/A3 P2_4/A4 P2_5/A5 P2_6/A6 P2_7/A7 VSS P3_0/A8 VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG P9_6/ANEX1 P9_5/ANEX0
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40
M16C/30P Group
39 38 37 36 35 34 33 32 31 30 29 28 27 26
P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT(1) P7_1/RXD2/SCL2/TA0IN(1) P7_2/CLK2/TA1OUT
NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2.
Figure 1.6
Pin Configuration (Top View)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 9 of 53
P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN
Package : PLQP0100KB-A (100P6Q-A)
M16C/30P Group
1. Overview
Table 1.6
Pin No. FP GP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Characteristics (1)
Control Pin Port
P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 TA2IN TA2OUT TA1IN TA1OUT TA0IN TA0OUT CTS2/RTS2 CLK2 RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RDY/CLKOUT ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 NMI INT2 INT1 INT0 P8_7 P8_6 TB2IN TB1IN TB0IN
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
ANEX1 ANEX0
Bus Control Pin
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
Table 1.7
Pin Characteristics (2)
Port
P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 KI3 KI2 KI1 KI0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 INT4 INT3
Pin No. Control Pin FP GP
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 VCC2 61 62 VSS 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 AVSS 95 96 VREF 97 AVCC 98
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P9_7
ADTRG
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
1.6
Pin Description
Pin Description (1)
Pin Name VCC1, VCC2 VSS AVCC AVSS RESET CNVSS I/O Type Description I Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 = VCC2. I Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. I The microcomputer is in a reset state when applying "L" to the this pin. I Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. I Switches the data bus in external memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. I/O Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. I/O Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. O Output address bits (A0 to A19). O O Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program. * WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space. * WR, BHE and RD are selected The WR signal becomes "L" by writing data in an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. ALE is a signal to latch the address. While the HOLD pin is held "L", the microcomputer is placed in a hold state. In a hold state, HLDA outputs a "L" signal. While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state.
Table 1.8
Signal Name Power supply input Analog power supply input Reset input CNVSS
External data bus width select input
BYTE
Bus control pins
D0 to D7 D8 to D15 A0 to A19 CS0 to CS3 WRL/WR WRH/BHE RD
ALE HOLD HLDA RDY I : Input O : Output
O I O I
I/O : Input and output
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
1. Overview
Table 1.9
Signal Name Main clock input Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A
Pin Description (2)
Pin Name XIN XOUT XCIN XCOUT CLKOUT INT0 to INT4 NMI KI0 to KI3 TA0OUT to TA2OUT TA0IN to TA2IN TB0IN to TB2IN CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK2 RXD0 to RXD2 TXD0 to TXD2 CLKS1 SDA0 to SDA2 SCL0 to SCL2 I/O Type I O I O O I I I I/O I I I O I/O I O O I/O I/O I I I I/O I I/O Description I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To use the external clock, input the clock from XCIN and leave XCOUT open. The clock of the same cycle as fC, f8, or f32 is outputted. Input pins for the INT interrupt. Input pin for the NMI interrupt. Input pins for the key input interrupt. These are timer A0 to timer A2 I/O pins. (however, the output of TA0OUT for the N-channel open drain output.) These are timer A0 to timer A2 input pins. These are timer B0 to timer B2 input pins. These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data output pins. (however, TXD2 for the N-channel open drain output.) This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (however, SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.) Applies the reference voltage for the A/D converter. Analog input pins for the A/D converter. This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_0 and P7_1 for the N-channel open drain output.)
Timer B Serial interface
I2C mode
Reference voltage input A/D converter
VREF AN0 to AN7, AN0_0 to AN0_7 ADTRG ANEX0 ANEX1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4, P8_6, P8_7 P8_5
I/O port
I/O I
I/O ports having equivalent functions to P0. Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register.
Input port I : Input
O : Output
I/O : Input and output
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M16C/30P Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31 b15 b8 b7 b0
R2 R3
R0H R1H R2 R3 A0 A1 FB
R0L R1L Data Registers (1)
Address Registers (1) Frame Base Registers (1)
b0
b19
b15
INTBH
INTBL
Interrupt Table Register
b19
b0
PC
b15 b0
Program Counter
USP ISP SB
b15 b0
User Stack Pointer Interrupt Stack Pointer Static Base Register
FLG
b15 b8 b7 b0
Flag Register
IPL
UI
OB S Z DC
Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area
NOTES: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.2
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0".
2.8.3
Zero Flag (Z Flag)
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0".
2.8.4
Sign Flag (S Flag)
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0".
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1".
2.8.6
Overflow Flag (O Flag)
This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0".
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
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M16C/30P Group
3. Memory
3.
Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h SFR 00400h Internal RAM XXXXXh Reserved area 0F000h Internal ROM (data area) (3, 4) 0FFFFh 10000h External area 27000h Reserved area
Internal RAM Size 5 Kbytes 6 Kbytes 12 Kbytes Address XXXXXh 017FFh 01BFFh 033FFh Size 96 Kbytes 128 Kbytes 160 Kbytes 192 Kbytes 256 Kbytes Internal ROM
(5)
(1)
FFE00h
Special page vector table
FFFDCh
28000h External area D0000h Reserved area (2, 4) YYYYYh Internal ROM (program area) (5) FFFFFh FFFFFh
Undefined instruction
Overflow
BRK instruction Address match Single step Watchdog timer DBC NMI Reset
Address YYYYYh E8000h E0000h D8000h D0000h C0000h(6)
NOTES: 1. During memory expansion and microprocessor modes, can be used. 2. In memory expansion mode, can be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" . 5. When using the masked ROM version, write nothing to internal ROM area. 6. When the PM13 bit is set to "0", the address of Internal ROM becomes D0000h, and when the PM13 bit is set to "1", the address becomes C0000h.
Figure 3.1
Memory Map
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M16C/30P Group
4. Special Function Register (SFR)
4.
Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR information. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
SFR Information (1) (1)
Register Symbol After Reset
Processor Mode Register 0 (2) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register Address Match Interrupt Enable Register Protect Register
PM0 PM1 CM0 CM1 CSR AIER PRCR
00000000b(CNVSS pin is "L") 00000011b(CNVSS pin is "H")
00XXX0X0b 01001000b 00100000b 00000001b XXXXXX00b XX000000b
Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
WDTS WDC RMAD0
XXh 00XXXXXXb 00h 00h X0h 00h 00h X0h
Address Match Interrupt Register 1
RMAD1
DMA0 Source Pointer
SAR0
XXh XXh XXh XXh XXh XXh XXh XXh
DMA0 Destination Pointer
DAR0
DMA0 Transfer Counter
TCR0
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh XXh XXh XXh XXh XXh XXh XXh
DMA1 Destination Pointer
DAR1
DMA1 Transfer Counter
TCR1
DMA1 Control Register
DM1CON
00000X00b
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. The PM00 and PM01 bits do not change at software reset. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 033Fh
4. Special Function Register (SFR) SFR Information (2) (1)
Register Symbol After Reset
INT3 Interrupt Control Register UART1 BUS Collision Detection Interrupt Control Register UART0 BUS Collision Detection Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register
INT3IC U1BCNIC U0BCNIC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC
XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b
Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register
TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC
XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b
Flash Memory Control Register 1 (2) Flash Memory Control Register 0 (3)
FMR1 FMR0
0X00XX0Xb 00000001b
Peripheral Clock Select Register
PCLKR
00000011b
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. 3. This register is included in the flash memory version and one time flash version.
X : Nothing is mapped to this bit
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M16C/30P Group Table 4.3
Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh
4. Special Function Register (SFR) SFR Information (3) (1)
Register Symbol After Reset
Interrupt Factor Select Register 2 Interrupt Factor Select Register
IFSR2A IFSR
00XXXXXXb 00h
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh
NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.4
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh
4. Special Function Register (SFR) SFR Information (4) (1)
Register
Count Start Flag Clock Prescaler Reset Fag One-Shot Start Flag Trigger Select Register Up-Down Flag Timer A0 Register Timer A1 Register Timer A2 Register
Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2
After Reset 000XX000b 0XXXXXXXb 00XXX000b XXXX0000b XX0XX000b (2) XXh XXh XXh XXh XXh XXh
Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register
TB0 TB1 TB2 TA0MR TA1MR TA2MR
XXh XXh XXh XXh XXh XXh 00h 00h 00h
Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register
TB0MR TB1MR TB2MR
00XX0000b 00XX0000b 00XX0000b
UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh X0000000b
DMA0 Request Factor Select Register DMA1 Request Factor Select Register CRC Data Register CRC Input Register
DM0SL DM1SL CRCD CRCIN
00h 00h XXh XXh XXh
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. Bit 5 in the Up-down flag is "0" by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit
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M16C/30P Group Table 4.5
Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh
4. Special Function Register (SFR) SFR Information (5) (1)
Register Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset
A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
XXX000X0b 000X0XXXb 00000XXXb
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh 00h
Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Port Control Register
PUR0 PUR1 PUR2 PCR
00h 00000000b (2) 00000010b (2) 00h 00h
NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. At hardware reset, the register is as follows: * "00000000b" where "L" is inputted to the CNVSS pin * "00000010b" where "H" is inputted to the CNVSS pin At software reset, the register is as follows: * "00000000b" where the PM01 to PM00 bits in the PM0 register are "00b" (single-chip mode). * "00000010b" where the PM01 to PM00 bits in the PM0 register are "01b" (memory expansion mode) or "11b" (microprocessor mode). X : Nothing is mapped to this bit
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M16C/30P Group
5. Electrical Characteristics
5.
Electrical Characteristics
Table 5.1
Symbol VCC AVCC VI Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, VREF, XIN P7_0, P7_1 VO Output Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, XOUT P7_0, P7_1 Pd Topr Power Dissipation Operating Ambient Temperature When the Microcomputer is Operating One Time Flash Program Erase Flash Program Erase Tstg Storage Temperature -40CAbsolute Maximum Ratings
Parameter Supply Voltage(VCC1=VCC2) Condition VCC1=VCC2=AVCC VCC1=VCC2=AVCC Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V V
-0.3 to 6.5 -0.3 to VCC+0.3
V V
-0.3 to 6.5 300 -20 to 85 / -40 to 85 0 to 60 0 to 60 -65 to 150
V mW C
C
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M16C/30P Group
5. Electrical Characteristics
Table 5.2
Symbol VCC AVCC VSS AVSS VIH
Recommended Operating Conditions (1)
Parameter Supply Voltage (VCC1=VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P7_0, P7_1
Standard Min. 2.7 Typ. 5.0 VCC 0 0 0.8VCC 0.8VCC 0.5VCC 0.8VCC 0.8VCC 0 0 0 0 VCC VCC VCC VCC 6.5 0.2VCC 0.2VCC 0.16VCC 0.2VCC -10.0 -5.0 10.0 5.0 0 0 32.768 0 16 20xVCC1-44 50 16 Max. 5.5
Unit V V V V V V V V V V V V V mA mA mA mA MHz MHz kHz MHz
VIL
LOW Input Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, XIN, RESET, CNVSS, BYTE
IOH(peak) IOH(avg) IOL(peak) IOL(avg) f(XIN)
HIGH Peak Output Current HIGH Average Output Current LOW Peak Output Current LOW Average Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
Main Clock Input VCC=3.0V to 5.5V Oscillation VCC=2.7V to 3.0V Frequency (4) Sub-Clock Oscillation Frequency CPU Operation Clock
f(XCIN) f(BCLK)
NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85C / -40 to 85C unless otherwise specified. 2. The Average Output Current is the mean value within 100ms. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be -40mA max. The total IOH(peak) for ports P3, P4 and P5 must be -40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH(peak) for ports P8_6, P8_7 and P9 must be -40mA max. Set Average Output Current to 1/2 of peak. 4. Relationship between main clock oscillation frequency, and supply voltage.
Main clock input oscillation frequency
f(XIN) operating maximum frequency [MHz]
20 x VCC1-44MHz
16.0
10.0
0.0 2.7 3.0 5.5
VCC1[V] (main clock: no division)
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M16C/30P Group
5. Electrical Characteristics
Table 5.3
Symbol - INL
A/D Conversion Characteristics (1)
Parameter Resolution Integral Non-Linearity Error 10bit Measuring Condition VREF=VCC VREF= VCC= 5V VREF= VCC= 3.3V 8bit AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input 3 2 5 5 VREF=VCC VREF=VCC=5V, AD=10MHz VREF=VCC=5V, AD=10MHz 10 3.3 2.8 0.3 3.0 0 VCC VREF 40 Standard Min. Typ. Max. 10 5 Unit Bits LSB
7
LSB
VREF=VCC=5V, 3.3V VREF= VCC= 5V VREF= VCC =3.3V
2 5
LSB LSB
-
Absolute Accuracy
10bit
7
LSB
8bit - DNL - - RLADDER tCONV tCONV tSAMP VREF VIA Tolerance Level Impedance Differential Non-Linearity Error Offset Error Gain Error Ladder Resistance 10-bit Conversion Time, Sample & Hold Function Available 8-bit Conversion Time, Sample & Hold Function Available Sampling Time Reference Voltage Analog Input Voltage
VREF=VCC=5V, 3.3V
2
LSB k LSB LSB LSB k s s s V V
NOTES: 1. Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85C / -40 to 85C unless otherwise specified. 2. AD frequency must be 10 MHz or less. 3. When sample & hold function is disabled, AD frequency must be 250 kHz or more, in addition to the limitation in Note 2. 4. When sample & hold function is enabled, AD frequency must be 1MHz or more, in addition to the limitation in Note 2.
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M16C/30P Group
5. Electrical Characteristics
Table 5.4
Symbol - - - - - - - tPS -
Flash Memory Version Electrical Characteristics (1)
Parameter Program and Erase Endurance (2) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) 4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block Flash Memory Circuit Stabilization Wait Time Data Hold Time (4) 10 Standard Min. 100(3) 25 25 0.3 0.3 0.5 0.8 200 200 4 4 4 4 15 Typ. Max. Unit cycle s s s s s s s year
NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C (U3, U5) unless otherwise specified. 2. Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is 100, each block can be erased 100 times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 3. Maximum number of E/W cycles for which operation is guaranteed. 4. Topr = -40 to 85 C (U3) / -20 to 85 C (U5).
Table 5.5
Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics
Flash Read Operation Voltage VCC1=2.7 to 5.5 V (Topr = -40C to 85C (U3)
-20C to 85C (U5))
Flash Program, Erase Voltage VCC1 = 3.3 0.3 V or 5.0 0.5 (Topr = 0C to 60C )
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M16C/30P Group
5. Electrical Characteristics
Table 5.6
Symbol - - tPS -
One Time Flash Version Electrical Characteristics (1)
Parameter Program Endurance Word Program Time (VCC1=5.0V) One Time Flash Memory Circuit Stabilization Wait Time Data Hold Time (4) 10 50 Standard Min. Typ. Max. 1 500 15 Unit cycle s s year
NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C (U3, U5) unless otherwise specified. 2. Topr = -40 to 85 C (U3) / -20 to 85 C (U5).
Table 5.7
One Time Flash Version Program Voltage and Read Operation Voltage Characteristics
Flash Read Operation Voltage VCC1=2.7 to 5.5 V (Topr = -40C to 85C (U3)
-20C to 85C (U5))
Flash Program Voltage VCC1 = 3.3 0.3 V or 5.0 0.5 (Topr = 0C to 60C )
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M16C/30P Group
5. Electrical Characteristics
Table 5.8
Symbol td(P-R) td(R-S) td(W-S)
Power Supply Circuit Timing Characteristics
Parameter Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipation Mode Wait Mode Release Time Measuring Condition VCC=2.7V to 5.5V Standard Min. Typ. Max. 2 1500 1500 Unit ms s s
td(P-R)
Time for Internal Power Supply Stabilization During Powering-On
Recommended operation voltage VCC CPU clock
td(P-R)
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode Wait Mode Release Time
Interrupt for (a) Stop mode release or (b)Wait mode release CPU clock (a) (b)
td(R-S) td(W-S)
Figure 5.1
Power Supply Circuit Timing Diagram
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.9
Symbol VOH
HIGH Output Voltage HIGH Output Voltage
Electrical Characteristics(1)
Parameter
(1) Measuring Condition
IOH=-5mA
Standard Min. VCC-2.0 Typ. Max. VCC
Unit
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER LOWPOWER
V
VOH
IOH=-200A
VCC-0.3
IOH=-1mA IOH=-0.5mA With no load applied With no load applied IOL=5mA
VCC VCC VCC 2.5 1.6 2.0
V
VOH
HIGH Output Voltage
VCC-2.0 VCC-2.0
V V
HIGH Output Voltage
XCOUT
HIGHPOWER LOWPOWER
VOL
LOW Output Voltage LOW Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER LOWPOWER
V
VOL
IOL=200A
0.45
IOL=1mA IOL=0.5mA With no load applied With no load applied
V
VOL
LOW Output Voltage
2.0 2.0 0 0 0.2 0.2 1.0 2.5
V V
LOW Output Voltage
XCOUT
HIGHPOWER LOWPOWER
VT+-VT-
Hysteresis
TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2 RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 VI=5V
V V A
VT+-VTIIH
Hysteresis HIGH Input Current
5.0
IIL
LOW Input Current
VI=0V
-5.0
A
RPULLUP Pull-Up
Resistance
VI=0V
30
50 1.5 15
170
k M M V
RfXIN RfXCIN VRAM
Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode
2.0
NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN) =16MHz unless otherwise specified.
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M16C/30P Group
5. Electrical Characteristics
Table 5.10
Symbol ICC
Electrical Characteristics (2) (1)
Parameter Measuring Condition Mask ROM One Time Flash Flash Memory One Time Flash Flash Memory Program Flash Memory Erase Mask ROM One Time Flash
f(XIN)=16MHz No division f(XIN)=16MHz, No division f(XIN)=16MHz, No division f(XIN)=10MHz, VCC1=5.0V f(XIN)=10MHz, VCC1=5.0V f(XIN)=10MHz, VCC1=5.0V f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3)
Standard Min. Typ. 10 10 12 15 15 25 25 25 Max. 15 18 18
Unit mA mA mA mA mA mA A A A A A A A
Power Supply Current In single-chip (VCC1=VCC2=4.0V to 5.5V) mode, the output pins are open and other pins are VSS
350 25 420 7.5 2.0 0.8 3.0
Flash Memory
f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3)
Mask ROM One Time Flash Flash Memory
f(XCIN)=32kHz Wait mode (2), Oscillation capability High f(XCIN)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25C
A
NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=16MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists.
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.11
Symbol tc tw(H) tw(L) tr tf
External Clock Input (XIN input) (1)
Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. 62.5 25 25 15 15 Max. Unit ns ns ns ns ns
NOTES: 1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 5.12
Symbol tac1(RD-DB) tac2(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD)
Memory Expansion Mode and Microprocessor Mode
Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Setup Time RDY Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time 40 30 40 0 0 0 Standard Min. Max. (NOTE 1) (NOTE 2) Unit ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD Input Setup Time
NOTES: 1. Calculated according to the BCLK frequency as follows:
9 0.5x10 ----------------------- - 45 [ ns ] f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9 ( n - 0.5 )x10 ------------------------------------ - 45 [ ns ] f ( BCLK ) n is "2" for 1-wait setting.
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.13
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width
Timer A Input (Counter Input in Event Counter Mode)
Parameter Standard Min. 100 40 40 Max. Unit ns ns ns
Table 5.14
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.15
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 5.16
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 100 100 Max. Unit ns ns
Table 5.17
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 5.18
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 800 200 200 Max. Unit ns ns ns
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.19
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.20
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.21
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.22
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG Input Cycle Time ADTRG input LOW Pulse Width Standard Min. 1000 125 Max. Unit ns ns
Table 5.23
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 5.24
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 250 250 Max. Unit ns ns
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.25
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
Memory Expansion and Microprocessor Modes (for setting with no wait)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time 4 (NOTE 1) (NOTE 2) 40 0 40 See Figure 5.2 -4 25 0 25 -3 15 -3 0 (NOTE 2) 25 Standard Min. Max. 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 40 [ ns ] f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
30pF
Figure 5.2
Ports P0 to P10 Measurement Circuit
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.26 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time 4 (NOTE 1) (NOTE 2) 40 0 40 See Figure 5.2 -4 25 0 25 -3 15 -3 0 (NOTE 2) 25 Standard Min. Max. 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n - 0.5 )x10 ----------------------------------- - 40 [ ns ] n is "1" for 1-wait setting, f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input tr tw(H) tf tc tw(L)
tc(TA) tw(TAH) TAiIN input tw(TAL)
tc(UP) tw(UPH) TAiOUT input tw(UPL)
TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode th(TIN-UP) tsu(UP-TIN)
tc(TA)
TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Figure 5.3
Timing Diagram (1)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 36 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) RXDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D)
Figure 5.4
Timing Diagram (2)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
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M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD (Separate bus) WR, WRL, WRH (Separate bus) RDY input
tsu(RDY-BCLK) th(BCLK-RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD input
HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2
(1)
td(BCLK-HLDA)
Hi-Z
td(BCLK-HLDA)
NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register.
* Measuring conditions : * VCC1=VCC2=5V * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 5.5
Timing Diagram (3)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 38 of 53
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait) Read timing
VCC1=VCC2=5V
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD tac1(RD-DB)
(0.5 x tcyc-45)ns.max Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V
(0.5 x tcyc-40)ns.min
(0.5 x tcyc-10)ns.min
th(WR-DB)
Figure 5.6
Timing Diagram (4) Page 39 of 53
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access) Read timing
BCLK td(BCLK-CS)
25ns.max
VCC1=VCC2=5V
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD tac2(RD-DB)
(1.5 x tcyc-45)ns.max
DBi
Hi-Z
th(RD-DB) tsu(DB-RD)
40ns.min 0ns.min
Write timing
BCLK td(BCLK-CS)
25ns.max
th(BCLK-CS)
-3ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
-3ns.min
ADi BHE td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.7
Timing Diagram (5) Page 40 of 53
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Table 5.27
Symbol VOH HIGH Output Voltage
Electrical Characteristics (1)
Parameter
(1) Measuring Condition Standard Min. VCC-0.5 VCC-0.5 VCC-0.5 2.5 1.6 0.5 0.5 0.5 0 0 Typ. Max. VCC VCC VCC Unit
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH=-1mA P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
V
VOH
HIGH Output Voltage
XOUT
HIGHPOWER LOWPOWER
IOH=-0.1mA IOH=-50A With no load applied With no load applied
V V
HIGH Output Voltage XCOUT VOL LOW Output Voltage
HIGHPOWER LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL=1mA P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGHPOWER LOWPOWER
V
VOL
LOW Output Voltage XOUT LOW Output Voltage XCOUT
IOL=0.1mA IOL=50A With no load applied With no load applied
V V
HIGHPOWER LOWPOWER
VT+-VT-
Hysteresis
TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, RXD0 to RXD2, CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2 RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
0.2
0.8
V
VT+-VTIIH
Hysteresis HIGH Input Current
0.2 VI=3V
(0.7)
1.8
V A
4.0
IIL
LOW Input Current
VI=0V -4.0 A
RPULLUP Pull-Up Resistance RfXIN RfXCIN VRAM
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
50
100 3.0 25
500
k M M V
Feedback Resistance Feedback Resistance RAM Retention Voltage
XIN XCIN At stop mode 2.0
NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=10MHz no wait unless otherwise specified.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 41 of 53
M16C/30P Group
5. Electrical Characteristics
Table 5.28
Symbol ICC
Electrical Characteristics (2) (1)
Parameter Measuring Condition Mask ROM One Time Flash Flash Memory Flash Memory Program f(XIN)=10MHz No division f(XIN)=10MHz, No division f(XIN)=10MHz, No division f(XIN)=10MHz, VCC1=3.0V Standard Min. Typ. 8 8 8 12 12 22 25 Max. 11 13 13 Unit mA mA mA mA mA mA A
Power Supply Current In single-chip (VCC1=VCC2=2.7V to 3.6V) mode, the output pins are open and other pins are VSS
One Time f(XIN)=10MHz, Flash Program VCC1=3.0V Flash Memory Erase Mask ROM f(XIN)=10MHz, VCC1=3.0V f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) Flash Memory f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) Mask ROM One Time Flash Flash Memory f(XCIN)=32kHz Wait mode (2), Oscillation capability High f(XCIN)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25C
One Time Flash
25
A
350
A
25
A
420
A
6.0
A
1.8 0.7 3.0
A A
NOTES: 1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = -20 to 85C / -40 to 85C, f(XIN)=10MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 42 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.29
Symbol tc tw(H) tw(L) tr tf
External Clock Input (XIN input)
Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. (NOTE 2) (NOTE 3) (NOTE 3) (NOTE 4) (NOTE 4) Max. Unit ns ns ns ns ns
NOTES: 1. The condition is VCC1=VCC2=2.7 to 3.0V. 2. Calculated according to the VCC1 voltage as follows:
10 - 6 --------------------------------------- [ns] 20 x VCC1 - 44
3. Calculated according to the VCC1 voltage as follows:
10 --------------------------------------- x 0.4 [ns] 20 x VCC1 - 44
-6
4. Calculated according to the VCC1 voltage as follows:
- 10 x VCC1 + 45 [ns]
Table 5.30
Symbol tac1(RD-DB) tac2(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD)
Memory Expansion Mode and Microprocessor Mode
Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Setup Time RDY Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time 50 40 50 0 0 0 Standard Min. Max. (NOTE 1) (NOTE 2) Unit ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD Input Setup Time
NOTES: 1. Calculated according to the BCLK frequency as follows:
9 0.5x10 ----------------------- - 60 [ ns ] f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9 ( n - 0.5 )x10 ----------------------------------- - 60 [ ns ] f ( BCLK )
n is "2" for 1-wait setting.
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 43 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.31
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width
Timer A Input (Counter Input in Event Counter Mode)
Parameter Standard Min. 150 60 60 Max. Unit ns ns ns
Table 5.32
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (Gating Input in Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 5.33
Symbol tc(TA) tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in One-shot Timer Mode)
Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 300 150 150 Max. Unit ns ns ns
Table 5.34
Symbol tw(TAH) tw(TAL)
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 150 150 Max. Unit ns ns
Table 5.35
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP)
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 3000 1500 1500 600 600 Max. Unit ns ns ns ns ns
Table 5.36
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 2 500 500 Max. Unit s ns ns
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 44 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.37
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Timer B Input (Counter Input in Event Counter Mode)
Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns
Table 5.38
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 5.39
Symbol tc(TB) tw(TBH) tw(TBL)
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns
Table 5.40
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG Input Cycle Time ADTRG Input LOW Pulse Width Standard Min. 1500 200 Max. Unit ns ns
Table 5.41
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Serial Interface
Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time 0 100 90 Standard Min. 300 150 150 160 Max. Unit ns ns ns ns ns ns ns
Table 5.42
Symbol tw(INH) tw(INL)
External Interrupt INTi Input
Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 380 380 Max. Unit ns ns
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 45 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.43
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
Memory Expansion and Microprocessor Modes (for setting with no wait)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time 4 (NOTE 1) (NOTE 2) 40 0 40 See Figure 5.8 -4 30 0 30 0 25 0 0 (NOTE 2) 30 Standard Min. Max. 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 40 [ ns ] f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
30pF
Figure 5.8
Ports P0 to P10 Measurement Circuit
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 46 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = -20 to 85C / -40 to 85C unless otherwise specified) Table 5.44 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access)
Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time 4 (NOTE 1) (NOTE 2) 40 0 40 See Figure 5.8 -4 30 0 30 0 25 0 0 (NOTE 2) 30 Standard Min. Max. 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA)
NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n - 0.5 )x10 ----------------------------------- - 40 [ ns ] n is "1" for 1-wait setting, f(BCLK) is 12.5MHz or less. f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- - 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1-VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k, hold time of output "L" level is t = -30pF X 1k X In(1-0.2VCC1 / VCC1) = 6.7ns.
R DBi C
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 47 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tr tw(H) tf tc tw(L)
tc(TA) tw(TAH)
TAiIN input
tw(TAL)
tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (Up/down input) During Event Counter Mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) th(TIN-UP) tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN) tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
Figure 5.9
Timing Diagram (1)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 48 of 53
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK) tw(CKH)
CLKi
tw(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.10
Timing Diagram (2)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 49 of 53
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
VCC1=VCC2=3V
BCLK
RD (Separate bus) WR, WRL, WRH (Separate bus)
RDY input tsu(RDY-BCLK) th(BCLK-RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD-BCLK)
th(BCLK-HOLD)
HOLD input
HLDA output td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1)
Hi-Z
td(BCLK-HLDA)
NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register. Measuring conditions : * VCC1=VCC2=3V * Input timing voltage : Determined with VIL=0.6V, VIH=2.4V * Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 5.11
Timing Diagram (3)
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 50 of 53
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait) Read timing
VCC1=VCC2=3V
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD tac1(RD-DB)
(0.5 x tcyc-60)ns.max
DBi
Hi-Z
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 x tcyc-10)ns.min
ALE td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.12
Timing Diagram (4) Page 51 of 53
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
M16C/30P Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access) Read timing
BCLK td(BCLK-CS)
30ns.max
VCC1=VCC2=3V
th(BCLK-CS)
0ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD tac2(RD-DB)
(1.5 x tcyc-60)ns.max
DBi
Hi-Z
th(RD-DB) tsu(DB-RD)
50ns.min 0ns.min
Write timing
BCLK td(BCLK-CS)
30ns.max
th(BCLK-CS)
0ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
0ns.min
ADi BHE td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
(0.5 x tcyc-10)ns.min
th(WR-AD)
ALE td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR,WRL, WRH td(BCLK-DB)
40ns.max Hi-Z
th(BCLK-DB)
4ns.min
DBi td(DB-WR) tcyc= 1 f(BCLK)
(0.5 x tcyc-40)ns.min
th(WR-DB)
(0.5 x tcyc-10)ns.min
Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.13
Timing Diagram (5) Page 52 of 53
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
M16C/30P Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Symbol
Dimension in Millimeters Min 19.8 13.8 Nom 20.0 14.0 2.8 22.5 16.5 22.8 16.8 23.1 17.1 3.05 0 0.25 0.13 0 0.1 0.3 0.15 0.2 0.4 0.2 10 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8 Max 20.2 14.2
100
D 31 E A2 1 ZD Index mark 30 F
c
A2
HD HE A A1
A
bp A1 L e y *3 bp Detail F c
e y ZD ZE L
0.5
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
bp b1 HE E
Reference Symbol
*2
Dimension in Millimeters Min 13.9 13.9 Nom 14.0 14.0 1.4 15.8 15.8 16.0 16.0 16.2 16.2 1.7 0.05 0.15 0.1 0.20 0.18 0.09 0.145 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 1.0 0.65 0.20 0.15 0.25 Max 14.1 14.1
c1
c
D E Terminal cross section A2 HD ZE 100 26 HE A 1 Index mark ZD F 25 A1 bp b1 c A2 A c1
c
e A1 y e *3 bp L L1 Detail F x y ZD ZE L L1 x
Rev.1.22 Mar 30, 2007 REJ03B0088-0122
Page 53 of 53
REVISION HISTORY
M16C/30P Group Datasheet
Description
Rev. 0.70 0.80
Date Aug 26, 2004 Mar 18, 2005
Page - - - 2 4 8 20 21 22 28 First Edition issued
Summary development support tools -> development tools BCLK -> CPU clock Table 1.1 Performance Outline of M16C/30P Group Serial interface is revised. Figure 1.2 Type., Memory Size, and Package is partly revised. Table 1.4 Pin Detection (2) is partly revised. Note 2 Table 5.3 A/D Conversion Characteristics is partly revised. Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly revised. Table 5.5 Electrical Characteristics is revised. Table 5.19 Electrical Characteristics is revised. Table 1.1 Performance Outline of M16C/30P Group is partly revised. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised. Figure 1.3 Pin Configuration is partly revised. Figure 1.4 Pin Configuration is partly revised. Tables 1.3 to 1.4 Pin Characteristics are added. Table 1.5 Pin Description is revised. 3. Memory is partly revised. Table 4.1 SFR Information is partly revised. Table 4.5 SFR Information is partly revised Table 5.2 Recommended Operating Conditions is partly revised. Table 5.3 A/D Conversion Characteristics is partly revised. Note 1 is added in Table 5.6 External Clock Input (XIN input) Table 5.7 Memory Expansion Mode and Microprocessor Mode is added. Table 5.20 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 5.2 Ports P0 to P10 Measurement Circuit is added. Table 5.21 Memory Expansion Mode and Microprocessor Modes (for 1- to 3-wait setting and external area access) is added. Figure 5.5 Timing Diagram (3) is added. Figure 5.6 Timing Diagram (4) is added. Figure 5.7 Timing Diagram (5) is added. Note 1 to 4 are added in Table 5.23 External Clock Input (XIN input) Table 5.24 Memory Expansion Mode and Microprocessor Mode is added. Table 5.37 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 5.8 Ports P0 to P10 Measurement Circuit is added. Table 5.38 Memory Expansion Mode and Microprocessor Modes (for 1- to 3-wait setting and external area access) is added. Figure 5.11 Timing Diagram (3) is added.
1.00
Sep 01, 2005
2 4 5 6 7-8 9 14 15 19 21 22 25 28
29 32 33 34 36 39
40 43
C-1
REVISION HISTORY
Rev. Date
M16C/30P Group Datasheet
Description
Page 44 45
Summary Figure 5.12 Timing Diagram (4) is added. Figure 5.13 Timing Diagram (5) is added. Table 1.1 Performance Outline of M16C/30P Group is partly revised. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised. Table 1.3 Product Code of Mask ROM version Version for M16C/30P is added. Figure 1.3 Marking Diagram of Mask ROM Version for M16C/30P is added.
1.10
Oct 01, 2005
2 4 5
6 6 16 23 1.11 May 31, 2006 4 5 7
Figure 1.4 Marking Diagram of ROM -less Version for M16C/30P is added. Table 1.4 Product Code of ROM-less version for M16C/30P is added. Figure 3.1 Memory Map is partly added. Table 5.2 information is revised. 1.4 Product List information is revised. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly added. Table 1.4 Product Code of Flash Memory version and ROM-less version for M16C/30P is partly revised. Figure 1.4 Marking Diagram of Flash Memory version and ROM-less Version for M16C/30P (Top View) is partly added.
17 18 19 23 26
3. Memory information is revised. Figure 3.1 Memory Map is partly revised. Table 4.1 SFR Information(1) is partly revised. Table 4.2 SFR Information(2) is partly added. Table 5.1 Absolute Maximum Ratings information is revised. Table 5.4 Flash Memory Version Electrical Characteristics is added. Table 5.5 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is added. Table 5.7 Electrical Characteristics(1) is partly deleted. Table 5.8 Electrical Characteristics (2) is partly revised. Table 5.23 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised. Table 5.24 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised. Table 5.25 Electrical Characteristics (1) is partly deleted. Table 5.26 Electrical Characteristics (2) is partly revised. Table 5.41 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised. Table 5.42 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised.
28 29 33 34 40 41 45 46
C-2
REVISION HISTORY
Rev. 1.20 Date Oct 17, 2006 Page 1 2 4 5 7 17 19 23 27
M16C/30P Group Datasheet
Description Summary
Note is partly deleted. Table 1.1 Performance Outline of M16C/30P Group is partly added. Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is added. Table 1.4 Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P is partly added. Figure 3.1 Memory Map is partly added. Table 4.2 SFR Information (2) is partly added. Table 5.1 Absolute Maximum Ratings is partly added. Table 5.6 One Time Flash Version Electrical Characteristics and Table 5.7 One Time Flash Version Program Voltage and Read Operation Voltage Characteristics is added. Table 5.10 Electrical Characteristics (2) is partly added. Table 5.28 Electrical Characteristics (2) is partly added. Table 1.4 Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P is partly revised. Table 1.2 Product List (1) is partly revised. Table 1.3 Product List (2) is partly revised. Table 4.2 SFR Information (2) is partly revised.
30 42 1.21 1.22 Nov 02 2006 Mar 30, 2007 7 4 5 19
C-3
Sales Strategic Planning Div.
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